The incorporation of high dielectric constant materials into small geometry capacitors suitable for Gigabit scale DRAM introduces fabrication challenges relating to topography, electrode material patterning, reaction of high-epsilon materials with Si contact and ultimate density/scalability. Similar challenges pertain to the fabrication of ferroelectric memory cells for ferroelectric RAM (FRAM) and other non-volatile RAM (NVRAM). To date, most fabrication strategies for making non-planar memory cells (a category of devices including both capacitors or "dielectric memory cells" and ferroelectric memory cells) is that the dielectric or ferroelectric deposition process be a conformal one which leaves a uniformly thin coating of film over all features of the sample topography. This requirement for a conformal process (such as chemical vapor deposition) tends to limit the use of promising spin-on deposition techniques (such as sol-gel) which have a tendency to gap fill and planarize.
An example of a fabrication method incorporating a sol-gel deposited cell dielectric into a three-dimensional memory device is found in U.S. Pat. No. 5,081,559, issued on Jan. 14, 1992 to Fazan et al. In this method, two electrodes are formed sequentially, prior to sol-gel deposition of the cell dielectric material, and the gap defined by a disposable sidewall spacer.